This invention relates to a data processing system comprising an input-output processor having control memories with a hierarchical relationship.
A data processing system of the type described, includes a memory device, input-output devices, a first data path between the memory device and the input-output devices, and an input-output processor. The input-output device may be a disk memory device, a magnetic tape memory device, or a display device. The input-output processor comprises first through N-th control memory layers, where N represents an integer greater than one. Each of the first through the N-th control memory layers comprises at least one control memory connected to the first data path. That is, a hierarchy exists among the control memories.
The data processing system comprises a holding device for holding first through N-th firmware data corresponding to the first through the N-th control memory layers. The data processing system is for transferring input-output data between the memory device and the input-output devices through the first data path under control of the input-output processor when the first through the N-th firmware data are stored in the control memories of the first through the N-th control memory layers, respectively.
As will later be described, a conventional data processing system comprises, separately from the first data path, second data paths, each of which connects the holding device and each of the control memories of the first through the N-th control memory layers. The second data paths are used in transferring the first through the N-th firmware data to the control memories of the first through the N-th control memory layers, respectively.
The number of the second data paths is increased with an increase in the number of the control memory layers and with an increase in the number of the control memories of each control memory layer. Thus, provision of the second data paths renders hardware of the data processing system complicated.
When only one control memory is included in each control memory layer, the first through the N-th firmware data are successively stored in the control memories of the first through the N-th control memory layers through the second data paths, respectively. It will be assumed that an increased number of the control memories are included in the N-th control memory layer. In this case, the N-th firmware data are successively stored in the control memories of the N-th control memory layer through the second data path. A long time is wasted to complete storage of the firmware data in all control memories of the input-output processor when the number of the control memories of each control memory layer is increased.